R

rtl

Verible build container.

The FreeNest platform development.

A minimalist, workstation platform

The compute chiplet, of Kunminghu cores, a shared ARV-Q, and the Ventus GPGPU.

The compute chiplet, of Kunminghu cores and a shared ARV-Q.

The shared code for the I/O chiplet of the FreeDev APUs.

The shared codes for the L3 cache chiplet for the FreeDev APUs.

The FreeBird APU development.

The TrustBird APU development.

PyTCL allows control EDA tools directly from Python that use TCL.

Python Register InterFace Translation

A Free HardWare Design of minimalist RISC 8-bit processor core for your System-on-Chip. See ygrec8.com

A Libre library of customisable VHDL gate definitions and tools to help analyse, optimise, test and failproof digital ciruits.

Hardware integer divider module

Containerized Questa*-Intel® FPGA Edition Software.

Verible build container.

This is a test task of one of the companies, which I completed simply "for myself".

A Docker image with the ModelSim HDL simulator