R

riscv

Lup Yuen's Articles and Resume

FreeDev Foundation: Open-source RISC-V hardware for the public good.

The TrustBird APU development.

The FreeBird APU development.

The compute chiplet, of Kunminghu cores, a shared ARV-Q, and the Ventus GPGPU.

The compute chiplet, of Kunminghu cores and a shared ARV-Q.

The shared code for the I/O chiplet of the FreeDev APUs.

The shared codes for the L3 cache chiplet for the FreeDev APUs.

A minimalist, workstation platform

The FreeNest platform development.

RISC-Y: RISC-V-Inspired Siple Computer for You

Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).

A modern assembler with built-in debugging and unit testing capabilities, ideal for both project compilation and educational purposes. Supports architectures including x86-64, aarch64, riscv64, and loongarch64.

RISC-V C Baremetal Example

This project develops RISC-V processor implementations.

Laghu (meaning 'small' in Sanskrit) is a small operating system written for RISC V as an attempt to understand the architecture inspired by old-school Unix systems.

RISCV D1 Nehza gcc10 Toolchain for MangoPi MQ-Pro

A Riscv assembly language syntax highlighter

BL602 / BL604 IoT SDK featured in "The RISC-V BL602 Book" https://lupyuen.github.io/articles/book

For BL602 WiFi Reverse Engineering