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riscv

Lup Yuen's Articles and Resume

RISC-Y: RISC-V-Inspired Siple Computer for You

Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).

A modern assembler with built-in debugging and unit testing capabilities, ideal for both project compilation and educational purposes. Supports architectures including x86-64, aarch64, riscv64, and loongarch64.

RISC-V C Baremetal Example

This project develops RISC-V processor implementations.

Laghu (meaning 'small' in Sanskrit) is a small operating system written for RISC V as an attempt to understand the architecture inspired by old-school Unix systems.

RISCV D1 Nehza gcc10 Toolchain for MangoPi MQ-Pro

A Riscv assembly language syntax highlighter

BL602 / BL604 IoT SDK featured in "The RISC-V BL602 Book" https://lupyuen.github.io/articles/book

For BL602 WiFi Reverse Engineering

For BL602 WiFi Reverse Engineering

For BL602 WiFi Reverse Engineering

Just a enum for ELF header e_machine field