A

ASIC

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector

PyTCL allows control EDA tools directly from Python that use TCL.

Scheme (r6rs) library to manage ASIC Switch via libsai.so

A Free HardWare Design of minimalist RISC 8-bit processor core for your System-on-Chip. See ygrec8.com

A synchronous protocol for accessing an asynchronous digital Design-Under-Test (JTAG sans the hassles)

Toolchain for simulating and building FPGA projects.