S

SystemVerilog

This project implements and verifies a Synchronous FIFO (First In First Out) using SystemVerilog RTL and a complete UVM-based verification environment.

A UVM-based verification environment for a 32-bit ALU in SystemVerilog, ensuring that all arithmetic and logic operations work correctly under various scenarios.

An implementation of Simon Says in Verilog for Xilinx FPGA systems

PyTCL allows control EDA tools directly from Python that use TCL.

Python Register InterFace Translation

Containerized FlexLM license manager for Questa*-Intel® FPGA Edition Software.

Containerized Questa*-Intel® FPGA Edition Software.

Repositorio grupal DVVSD P2021

Repositorio Personal DVVSD P2021

Toolchain for simulating and building FPGA projects.

A Docker image with the ModelSim HDL simulator

My repo for work on lecture Digital Hardware Design (WS 19/20, Prof Dr Bruening)