Vivado

This is a small project to display the message ‘Hello World’ on a serial terminal using the UART communication of the Basys3 board.

Using containerized FlexLM license managers as systemd service units for serving FPGA/ASIC EDA software licenses that can be also used in CI/CD flow.

A simple COMmunication BLOCK with well know interfaces in the FPGA side

A Python package to use FPGA development tools programmatically. It is a mirror of https://github.com/PyFPGA/pyfpga, where the development is done. Documentation: https://pyfpga.github.io/pyfpga

Flexible 16-bit cryptographic co-processor written in VHDL and Verilog. From Assigment EE540 DCU Master in Electronic and Computer Engineering