R

RISC-V

This is the central "hub" project for the Mutually Assured Accountability (MAA) Framework. This repository contains the master README, which provides the unified vision, architecture, and links to all component projects.

Bare-Metal 'Guil-OS' (Electronics & Electricals Projects)

(x86 / Risc-V / Aarch64)

Education-friendly RISC-V based system emulator

Bootdisks and Linux images for SBCs and TV boxes.

A simple educational operating system from scratch.

Development environment useful for debugging RVV (RISC-V Vector) software without hardware with GDB.

Virtual machine for Yeti Project / RISC-V Virtual machine as library

https://ovsienko.info/D1/

x86 and RISC-V assembler

A basic RV32I core for practice.

RISC-V C Baremetal Example

native-blink_asm example for board SparkFun RED-V thing plus (CPU FE310). Based on https://github.com/platformio/platform-sifive/tree/develop/examples/native-blink_asm

A RISC-V simulator with an integrated debugger. Support full RV32IM instruction set, along with pseudo instruction and several environmental calls.

E203 with GSNN AI acclerate module

Simple RISC-V Disassembler based on RISC-V Sliderules Web Script

The Dumb Bootloader for RISC-V systems

This project develops RISC-V processor implementations.