V

VHDL

Hog (HDL-on-git) is a set of Tcl/Shell scripts plus a suitable methodology to handle HDL designs in a git repository. For more information, visit our documentation page: https://cern.ch/hog, or register to our newsletter: http://cern.ch/go/nBn8

Vendor-Independent, Fully Verified, Open Source VHDL Common Library

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector

Sensor project for the Tanuki IoT Platform: FPGA digital filter

A library to represent and manipulate Hardware Description Language (HDL) block designs in Python

https://hdl-block-design.readthedocs.io/en/latest/

The pytest-fusesoc plugin allows to use pytest to discover and run simulation targets defined in FuseSoC *.core files. Furthermore, test capabilities can be greatly increased with existing pytest plugins, pytest built-in features like fixtures, test parametrization @pytest.mark.parametrize, tests reporting and more.

Containerized GHDL - VHDL simulator with Python and C++ compiler.

VHDL implementation of the DShot protocol with native and AXI interface

Deterministic timer IP core in VHDL for precise time-based event generation, supporting configurable periods and synchronization mechanisms.

Running legacy Xilinx ISE FPGA software on a MacOS system (including Apple Silicon) using Docker.

VHDL examples for use in D-H-EHE-SOC class

GateMateA1 Personal Computer, based on Olimex GateMateA1-EVB board

Toolbox of useful modules for CCSDS-compliant VHDL projects

Open source implementation of a universal CCSDS-compliant TM/TC Front-end for semi-professional satellite Ground Stations

Open Source implementation of an On-Board CCSDS Stack (OSI Layer 2)

BProC (Basic Processor Compiler) is a small customizable instruction set compiler for basic processor design, intended for educational purposes.

PyTCL allows control EDA tools directly from Python that use TCL.