V

VHDL

Hog (HDL-on-git) is a set of Tcl/Shell scripts plus a suitable methodology to handle HDL designs in a git repository. For more information, visit our documentation page: https://cern.ch/hog, or register to our newsletter: http://cern.ch/go/nBn8

A library to represent and manipulate Hardware Description Language (HDL) block designs in Python

https://hdl-block-design.readthedocs.io/en/latest/

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector

Containerized GHDL - VHDL simulator with Python and C++ compiler.

Running legacy Xilinx ISE FPGA software on a MacOS system (including Apple Silicon) using Docker.

A Free HardWare Design of minimalist RISC 8-bit processor core for your System-on-Chip. See ygrec8.com

Containerized FlexLM license manager for Questa*-Intel® FPGA Edition Software.

Containerized Questa*-Intel® FPGA Edition Software.

A collection of Perl scripts for digital design simulation and FPGA synthesis automation. It supports Verilog, VHDL and mixed language (Verilog + VHDL) designs.

A Docker image with the ModelSim HDL simulator

Projet de chiffrement AES en vhdl, dans le cadre de la formation ISMIN de l'école des Mines de St-Etienne.

Acoustic levitation on SoC FPGA (DE0-Nano-SoC)

https://youtu.be/p1Vm4cL4aUA