V

VHDL

Hog (HDL-on-git) is a set of Tcl/Shell scripts plus a suitable methodology to handle HDL designs in a git repository. For more information, visit our documentation page: https://cern.ch/hog, or register to our newsletter: http://cern.ch/go/nBn8

The pytest-fusesoc plugin allows to use pytest to discover and run simulation targets defined in FuseSoC *.core files. Furthermore, test capabilities can be greatly increased with existing pytest plugins, pytest built-in features like fixtures, test parametrization @pytest.mark.parametrize, tests reporting and more.

Vendor-Independent, Fully Verified, Open Source VHDL Common Library

A library to represent and manipulate Hardware Description Language (HDL) block designs in Python

https://hdl-block-design.readthedocs.io/en/latest/

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector

Sensor project for the Tanuki IoT Platform: FPGA digital filter

VHDL implementation of the DShot protocol with native and AXI interface

Deterministic timer IP core in VHDL for precise time-based event generation, supporting configurable periods and synchronization mechanisms.

PyTCL allows control EDA tools directly from Python that use TCL.

Generic UART with parity

Nand2Tetris implementation in VHDL

Estrin's scheme is an algorithm for numerical evaluation of polynomials.

A simple VHDL project to monitor a serial port for ongoing communication.

The source code of all IEEE packages. Development of future opensource.ieee.org/vasg/Packages releases.

Webpage: http://wilferciro.gitlab.io/sintel Documentation: https://sintel.readthedocs.io/en/latest/