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rtl

Python Register InterFace Translation

The pytest-fusesoc plugin allows to use pytest to discover and run simulation targets defined in FuseSoC *.core files. Furthermore, test capabilities can be greatly increased with existing pytest plugins, pytest built-in features like fixtures, test parametrization @pytest.mark.parametrize, tests reporting and more.

Deterministic timer IP core in VHDL for precise time-based event generation, supporting configurable periods and synchronization mechanisms.

PyTCL allows control EDA tools directly from Python that use TCL.

Wrapper for FPGA toolchain tools