V

VHDL

A Libre library of customisable VHDL gate definitions and tools to help analyse, optimise, test and failproof digital ciruits.

Containerized FlexLM license manager for Questa*-Intel® FPGA Edition Software.

Containerized Questa*-Intel® FPGA Edition Software.

The source code of all IEEE packages. Development of future opensource.ieee.org/vasg/Packages releases.

Solutions for list with basic tasks with concurrent operations for behavioral simulation.

A collection of Perl scripts for digital design simulation and FPGA synthesis automation. It supports Verilog, VHDL and mixed language (Verilog + VHDL) designs.

I implemented on a basys3 FPGA board a hardware projects which consists of basic arithmetic operations such as subtraction, addition, multiplier and division

Generic binary to 7-segment display driver

A VHDL synthesizable and behavioral FIFO design.

Toolchain for simulating and building FPGA projects.

repo for 487 code with a twist: hopefully you will be able to pull from it.

A stack-based 16-bit CPU written in VHDL (with pt-br docs)

An 16bit CPU written in VHDL, compile with GHDL.

VHDL project for a digital clock with the alarm functionality