RISC-V: Fast case for address translation

What

Improves performance of address translation

• addiw-wrong: For every instruction, perform a single address translation, assuming the whole instruction is in the same page. (This is wrong because the instruction is not guaranteed to be 4-byte aligned, thus can be split between pages)
• addiw-correct-slow: The simple fix is to just run two address translations, one for each half of the instruction (2 bytes each). This is correct since the address is guaranteed to be a multiple of 2, thus being in the same page.
• addiw-correct-fast: Perform a check for each instruction: If the address is a multiple of 4, then one address translation is enough, otherwise, we need to perform two, one for each half of the instruction. This brings back performance within 3% of the original (wrong) approach.

How

Instruction address is alwys 2-bytes aligned (multiple of 2), and this forces us to translate separately the first 2 bytes and the last 2 bytes of the instruction to cover the case of the two halfs being on separate virtual pages.

However, if the address is 4-byte aligned (multiple of 4), then we are guaranteed that all 4 bytes are in the same virtual page, meaning we can skip the address translation stage for the last 2 bytes.

Manually testing the MR

cd src/risc_v && cargo test

Checklist

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