RISC-V: Add CSR field declarations

What

The primary modification is located in the src/risc_v/interpreter/src/machine_state/csregisters/fields.rs file. This change involves expanding the CSR-field macro such that it consolidates all fields into a single type. By arranging fields sequentially, it eliminates the requirement to define bit offsets individually. Additionally, the width of a field is now determined by the type of the field itself.

The remainder of the changes just follow the use of the amended macros.

Why

Ultimately the goal of this MR is to establish a basis for strongly-typed CSRs. There is still an escape hatch where one can just read and write u64 into control and state registers, but hopefully we can get rid of this escape mechanism eventually.

Manually testing the MR