RISC-V: I-ext: AUIPC

What

Implement the AUIPC instruction from the RV32I base RISC-V ISA. (Section 2.4)

Why

Support running RISC-V executables with an in-house interpreter for better PVM support.

How

Extend HartState with run_auipc() method. Instructions should be implemented on the lowest state scope-wise. (MachineState > HartState > XRegister / FRegister / CSRregisters)

Manually testing the MR

cd src/risc_v/machine_state && cargo test

Checklist

• Document the interface of any function added or modified (see the coding guidelines)
• Document any change to the user interface, including configuration parameters (see node configuration)
• Provide automatic testing (see the testing guide).
• For new features and bug fixes, add an item in the appropriate changelog (docs/protocols/alpha.rst for the protocol and the environment, CHANGES.rst at the root of the repository for everything else).
• Select suitable reviewers using the Reviewers field below.
• Select as Assignee the next person who should take action on that MR