Refactor: hardware_t rewritten as a proper class.

This MR refactors the hardware_t type to be a proper class, such that one has the possibility to initialise it with other cache sizes. It also adds documentation.

Whilst the defaults for cache data size and line sizes are quite common, my M1 Mac has l1 cache specs that are twice the size for example:

hw.l1dcachesize: 65536 i.e. 64 kB
hw.cachelinesize: 128 bytes

(found with sysctl -a | grep 'cache'). This raises the question of whether we should make l1 data cache size and line size input variables, such that one can straightforwardly test optimisation for different hardware.