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#2842: RISC-V RVV1.0 support

Kseniya Zaytsevarequested to merge
kseniya.zaytseva/eigen:riscv-rvv1.0 into master

This patch adds support for RISCV's vector extension RVV1.0. The implementation is based on previously implemented ARM SVE support.

  • For now, you can only enable support for RVV1.0 explicitly by defining -DEIGEN_RISCV64_USE_RVV10
  • For use in Eigen we fix vector register size at compile-time -> You must set zvl into -march flag (for example, set zvl to 128 bits: -march=rv64gcv_zvl128b) and set -mrvv-vector-bits=zvl to make zvl not only the minimum vector length, but also the maximum
  • Supports vectors length from 128 to 1024
  • This PR introduces the PacketXf, PacketXi, PacketXd, PacketXl, PacketXcf, PacketXcd, PacketXh, PacketXs package types for packets of float, int32_t, double, int64_t, complex<float>, complex<double>, _Float16, int16_t respectively. The size of these packets depends on the RVV vector length
  • As a baseline it uses LMUL=1. Additional LMUL=4 support for LinearPacketType, InnerPacketType, Redux, and apply_rotation_in_the_plane
  • Also added support for scalar Eigen::half which is a scalar wrapper around the _Float16 type for RISC-V. Support for scalar and vector _Float16 is determined dynamically when the Zfh and Zvfh extensions are detected.
Edited by Kseniya Zaytseva

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