Support RISC-V and RISC-V Vector Extension (RVV)

Describe the feature you would like to be implemented.

We already support NEON and other low level ISA vector math, it makes sense that the RISC-V Vector (RVV) ISA Extension is something that we support as well.

Would such a feature be useful for other users? Why?

It would be useful to anyone building vectorized math code on the RISC-V architecture.

Any hints on how to implement the requested feature?

I imagine RISC-V Vector support would need to be added under /Eigen/src/Core/arch/.

Additional resources

https://github.com/riscv/riscv-v-spec/tree/master

SIMD Everywhere Optimization from ARM NEON to RISC-V Vector Extensions https://github.com/simd-everywhere/simde ^ A project that automatically converts neon to rvv intrinsics (not saying this is the approach to take, but it was pretty much the only resource that popped up when searching risc-v vector and eigen on a search engine)

https://riscv.org/wp-content/uploads/2018/05/15.20-15.55-18.05.06.VEXT-bcn-v1.pdf