Script generating symbols for Xilinx FPGA

This MR continues !293 (closed)

Intro

Xilinx has CSV files describing FPGA pinout (https://www.xilinx.com/support/package-pinout-files.html). This scripts generates symbols from those files.

Some background:

• Xilinx FPGA pins are divided into banks
• Each bank can be powered separately (from 1.2V to 3.3V)
• Most of pins are general purpose and bidirectional
• There are some dedicated pins (like reset, JTAG, config clk, etc). All of them are placed into bank 0
• Each FPGA has at least 3 power rails - VCCINT, VCCAUX, VCCBRAM each comes from several pins. Full-featured devices (like Zynq-7000) can have up to 10 power rails.
• There is always huge amount of GND pins. Up to 25% of package are GND pins.
• Total number of I/O pins >100

This scripts generates multi-unit kicad symbol, each KiCAD unit = FPGA Bank

Examples

Small FPGA - Spartan-7 (XC7S6-CPGA196) Medium FPGA - Artix-7 (XC7A12-CSG325) Large FPGA - Artix-7 (XC7A200-FFG1156) Zynq-7000 (XC7Z015-CLG485) Example of power bank routing:

Current progress:

• CSV parsing and pin extraction (checked for Spartan-7 family).
• Pin grouping by banks and function
• Symbol generation and pin layout
• Electrical types
• VCC* and GND pin stacking
• Footprints
• Adopted for Spartan-7, Artix-7, Zynq-7000 families
• Ported to v6
• Adopted for Kintex-7, Virtex-7, Artix-UltraScale+, Kintex-UltraScale(+), Virtex-UltraScale(+) families