[WIP] Script generating symbols for Xilinx FPGA

Created by: ObKo

Intro

Xilinx has CSV files describing FPGA pinout (https://www.xilinx.com/support/package-pinout-files.html). This scripts generates symbols from those files, similar to current STM32 generator.

Some background:

• Xilinx FPGA pins are divided into banks
• Each bank can be powered separately (from 1.2V to 3.3V)
• Most of pins are general purpose and bidirectional
• There are some dedicated pins (like reset, JTAG, config clk, etc). All of them are placed into bank 0
• Each FPGA has at least 3 power rails - VCCINT, VCCAUX, VCCBRAM each comes from several pins.
• There is always huge amount of GND pins.
• Total number of I/O pins >100

This scripts generates multi-unit kicad symbol, each KiCAD unit = FPGA Bank

Example

Here you can see generated symbol for xc7s6 FPGA in ftgb196 package:

Bank 0 is on top and contains all dedicated pins and common power rails. Other two units - Bank 14 and Bank 34 with 50 I/O and power.

Current progress:

• CSV parsing and pin extraction (checked for Spartan-7 family).
• Pin grouping by banks and function
• Symbol generation and pin layout
• Electrical types
• VCC* and GND pin stacking
• Footprint generation - should be synced to current PRs in KiCAD libraries: https://github.com/KiCad/kicad-footprints/issues/1560
• Adopt for families other than Spartan-7