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Overview
Active
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28MHz
953a0796
·
Latch data read inside the 28MHz sram cycle
·
Aug 29, 2019
legacy_timing
b56804a9
·
Enable ula contention for 48k and 128k timing
·
Sep 18, 2019
BUILD
4493c4ca
·
Core number back to 3.00.00 - SMS requires it :-/
·
Oct 06, 2019
cpu_wait_bug
91073318
·
28MHz: Insert wait state for all memory reads instead of just instruction fetch
·
Nov 02, 2019
divmmc
ac5d6b7a
·
divmmc incomplete
·
Jan 08, 2020
interrupt
5dbdcbf7
·
Update nextreg documentation
·
Jul 21, 2020
minor
80ffd66d
·
NEXTREG: Reserve nextreg 0x24 for compatibility with legacy software
·
Feb 27, 2021
cherry-pick-f870a63c
f2b6a55f
·
Interrupt acknowledge fixes
·
Apr 12, 2021
!6
cherry-pick-f1bfb957
d168b465
·
Port the auto-wait logic fix
·
Apr 12, 2021
!7
cherry-pick-dbbc161e
8ae964b6
·
Fix RLD, RRD cycles
·
Apr 13, 2021
!8
sram_memory_cycle
c6c19383
·
Center write signal in sram memory cycle, latch read into appropriate port at end of cycle
·
Apr 14, 2021
EMC
ce8f6fe2
·
Adjust constraints for issue 3 boards
·
Feb 13, 2022
DIVMMC
b8e15709
·
Register initialization error
·
Apr 05, 2022
ISSUE_4
1a711c9a
·
CORE VERSION 3.02.00
·
Jun 15, 2023
HDMI
78a6ee50
·
CORE VERSION 3.02.01
·
Sep 07, 2023
master
default
protected
78a6ee50
·
CORE VERSION 3.02.01
·
Sep 07, 2023
30202
74eeee31
·
Missing file from last commit
·
Apr 13, 2024