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Active branches
30202
74eeee31
·
Missing file from last commit
·
Apr 13, 2024
Stale branches
28MHz
953a0796
·
Latch data read inside the 28MHz sram cycle
·
Aug 29, 2019
legacy_timing
b56804a9
·
Enable ula contention for 48k and 128k timing
·
Sep 18, 2019
BUILD
4493c4ca
·
Core number back to 3.00.00 - SMS requires it :-/
·
Oct 06, 2019
cpu_wait_bug
91073318
·
28MHz: Insert wait state for all memory reads instead of just instruction fetch
·
Nov 02, 2019
divmmc
ac5d6b7a
·
divmmc incomplete
·
Jan 08, 2020