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Verilog Utilty Modules

Project information

Collection of utility modules written in Verilog

verilog FPGA random-numbe... gpio counter timer clock-divider PWM pulse-width-... adder random hardware

63 Commits
1 Branch
0 Tags

README
CERN Open Hardware Licence Version 2 - Weakly Reciprocal

Created on

November 20, 2020

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