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  • 10-updating-the-xdc-file-to-use-the-switches-and-buttons-available-in-arty-a7-boards
  • enable-vajrasim
  • master default protected
  • riscv-plic-upgrade
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Created with Raphaël 2.2.028Jul18May4222Apr2119171215Mar3125Feb24Jan2359Dec8412Nov13Oct7129Sep15128Aug24232221201964328Jul2625Update README.rst with memory map table fixmastermasterchange baud when compiled with simulateenable-vajrasimenable-vajrasimupdated READMEadding simulation configenabled sim without debuggeradding verilator target and collateral filesignore verilator artifactsbscan2e is used only for sunth. disable for simMerge branch 'eth-pin-fix' into 'master'eth ping patchesMerge branch 'master' into riscv-plic-upgraderiscv-plic-upgr…riscv-plic-upgradeMerge branch 'eth0-parashu' into 'master'updated plic and ethernet connectionsMerge branch 'master' into riscv-plic-upgradeMerge branch '27-update-in-mcs-file' into 'master'Update mcs/READMEupdate in i2cMerge branch 'i2c_hw_fix' into 'master'i2c changes for e32delaying enable signal as wellupdated fpga_top and constraints for eth on parashuadding delay of 10 registers on the sda pathintegration of eth0 on parashuUpdate mcs/vajra/vajra-01032021.bit, mcs/vajra/vajra-01032021.mcs filesupdated memory map for plicintegrated new plicMerge branch 'eth10' into 'master'Eth10Removed old mcs and bit filesUpdate README.rstMerge branch 'M_Kapil_Shyam-master-patch-30634' into 'master'Merge branch 'M_Kapil_Shyam-master-patch-93439' into 'master'Updating Readme.rstUpdating FPGA Board Connector Mappingupdated mcs and bit filesadd ethernet lite in readme for 100TMerge branch '20-modifying-the-gpio-pin-mapping' into 'master'Updating FPGA Board Connector MappingModifying GPIO pinsadded mcs files to repo