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platform/x86/intel/pmc: Fix Arrow Lake U/H NPU PCI ID

JIRA: https://issues.redhat.com/browse/RHEL-23894

commit f2eae58c4428bd792c8e91e3666ab0718d87b44a
Author: Todd Brandt todd.e.brandt@intel.com
Date: Tue May 20 03:45:55 2025 -0700

platform/x86/intel/pmc: Fix Arrow Lake U/H NPU PCI ID  

The ARL requires that the GMA and NPU devices both be in D3Hot in order  
for PC10 and S0iX to be achieved in S2idle. The original ARL-H/U addition  
to the intel_pmc_core driver attempted to do this by switching them to D3  
in the init and resume calls of the intel_pmc_core driver.  

The problem is the ARL-H/U have a different NPU device and thus are not  
being properly set and thus S0iX does not work properly in ARL-H/U. This  
patch creates a new ARL-H specific device id that is correct and also  
adds the D3 fixup to the suspend callback. This way if the PCI devies  
drop from D3 to D0 after resume they can be corrected for the next  
suspend. Thus there is no dropout in S0iX.  

Fixes: bd820906ea9d ("platform/x86/intel/pmc: Add Arrow Lake U/H support to intel_pmc_core driver")  
Signed-off-by: Todd Brandt <todd.e.brandt@intel.com>  
Link: https://lore.kernel.org/r/a61f78be45c13f39e122dcc684b636f4b21e79a0.1747737446.git.todd.e.brandt@intel.com  
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>  
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>  

Signed-off-by: David Arcari darcari@redhat.com

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