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[AMDSERVER 9.4 Feature] CXL Updates for Turin

John W. Linville requested to merge linville-rh/centos-stream-9-linville:RHEL-10040 into main

CXL features required by AMD for RHEL 9.4.

Preliminary testing provided by AMD: "testing has completed and everything appears to be working as expected."

  cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()
  cxl/port: Fix NULL pointer access in devm_cxl_add_port()
  cxl/core/regs: Add @dev to cxl_register_map
  cxl/acpi: Probe RCRB later during RCH downstream port creation
  cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
  cxl: Rename member @dport of struct cxl_dport to @dport_dev
  cxl: Rename 'uport' to 'uport_dev'
  cxl/pci: Refactor component register discovery for reuse
  cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
  cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
  cxl/port: Remove Component Register base address from struct cxl_dport
  cxl/regs: Remove early capability checks in Component Register setup
  cxl/mem: Prepare for early RCH dport component register setup
  cxl/pci: Early setup RCH dport component registers from RCRB
  cxl/port: Store the port's Component Register mappings in struct cxl_port
  cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
  cxl/core/regs: Rename @dev to @host in struct cxl_register_map
  cxl/port: Fix @host confusion in cxl_dport_setup_regs()
  cxl/port: Fix cxl_test register enumeration regression

JIRA: https://issues.redhat.com/browse/RHEL-10040

Conflicts in a few minor places due to this set of commits largely being applied out of order from upstream, due to RHEL maintainer concerns.

Signed-off-by: John W. Linville linville@redhat.com

Edited by John W. Linville

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