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cacheinfo: Fix sleep in atomic context on PREEMPT_RT kernels

Bugzilla: https://bugzilla.redhat.com/2180619

This MR changes the cacheinfo memory allocation behavior to avoid a
kmalloc in atomic context during initialization, which would otherwise
trigger a splat on PREEMPT_RT kernels.

Originally, cacheinfo memory corresponding to secondary CPUs was
allocated by code running on the secondary CPU itself. For arm64 CPUs,
this makes it possible to detect the number of caches by looking at
local CPU registers (e.g. clidr_el1) and size the allocated memory
accordingly. Otherwise, the information must be provided by the DT or
ACPI tables. The problem is that cacheinfo memory allocation happens
very early for secondary CPUs, while the CPU is still in non preemptible
context. On PREEMPT_RT kernels, kmalloc can sleep, even with GFP_ATOMIC.

To address this issue, multiple patches and patch series have been
ported from upstream. To summarize, this MR has 3 major parts:

  1. A patch series that moves cacheinfo memory allocation to the
    primary CPU when the number of caches is described in the DT or
    ACPI tables. In the absence of such information, memory is still
    allocated on the secondary CPU.
  2. A patch series that allocates cacheinfo memory on the primary CPU
    even when the DT/ACPI info is missing and assumes that secondary
    CPUs have the same number of caches as the primary CPU, which is
    true for symmetric CPUs. Detection still runs on the secondary
    CPU, and a correction (reallocation) is applied if the initial
    guess proves to be wrong.
  3. A patch series that fixes some corner cases and ensures the number
    of shared caches (between CPUs) is always accounted for correctly
    when automatic detection is used on arm64 CPUs.

The rest of the patches in this MR are support patches to make the
above patch series apply cleanly to the CentOS Stream 9 kernel and
compile and work as expected.

Ultimately, this MR aims to eliminate the kmalloc splat on PREEMPT_RT
kernels without requiring additional cacheinfo related information to be
added to DT/ACPI on systems with symmetric CPUs.

Signed-off-by: Radu Rendec rrendec@redhat.com

Edited by Radu Rendec

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