Feature: Improve overall zhinst backend timing

Explanation of changes

#88 (closed) Solves

• [Issue][General] Shift waveform start inside the waveform itself based on t0 to compensate for clock misalignment.
• [Issue][General] Reduce rounding errors when converting from time- to clock domain.
• [Issue][HDAWG] Compensate for sequencer operation clock durations to improve sequencer timing accuracy.
• [Issue][General] Acquisition timing misalignment when using HDAWG marker to trigger UHFQA.

Motivation of changes

• Unified the sequencer timing constraints and corrections for the UHFQA and HDAWG in the get_execution_table function. Here all details of clock rounding and waveform corrections, such as shifting, resizing are doing.
• Added the length property to the CommandTable json containing the original length of the waveform before corrections to enable closely aligned waveforms.
• Added device specific instruction clock cycle timing. The UHFQA and HDAWG differ.

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Merge checklist

See also merge request guidelines

• Merge request has been reviewed and approved by a project maintainer.
• Merge request contains a clear description of the proposed changes and the issue it addresses.
• Merge request made onto appropriate branch (develop for most MRs).
• New code is fully tested.
• New code is documented and docstrings use numpydoc format.
• CI pipelines pass
  • black code-formatting passes (gitlab-ci),
  • test suite passes (gitlab-ci),
  • no degradation in code-coverage (codacy),
  • no (serious) new pylint code quality issues introduced (codacy),
  • documentation builds succesfully (readthedocs).