ppc64: Implement the remaining PowerISA v3.1 instructions

Goal

Add support to the remaining PowerISA v3.1 instructions in TCG.

Technical details

QEMU is missing the following vector instructions:

• vcmp[su]q: Vector Compare Signed/Unsigned Quadword (Implemented in b58f3931)
• vcmpequq: Vector Compare Equal Unsigned Quadword (Implemented in 7b3da08e)
• vcmpgt[su]q: Vector Compare Greater Than Signed/Unsigned Quadword (Implemented in 50449ae4)
• vextsd2q: Vector Extend Sign Doubleword to Quadword (Implemented in acf43b34)
• vexpand[bhwdq]m: Vector Expand Byte/Halfword/Word/Doubleword/Quadword Mask (Implemented in 5f1470b0)
• vextract[bhwdq]m: Vector Extract Byte/Halfword/Word/Doubleword/Quadword Mask (Implemented in 17868d81)
• mtvsr[bhwdq]m: Move to VSR Byte/Halfword/Word/Doubleword/Quadword Mask (Implemented in 9193eaa9)
• vcntmb[bhwd]: Vector Count Mask Bits Byte/Halfword/Word/Doubleword (Implemented in 95f1ee28)
• vrlq: Vector Rotate Left Quadword (Implemented in aa0f34ec)
• vrlqmi: Vector Rotate Left Quadword then Mask Insert (Implemented in 7e5947df)
• vrlqnm: Vector Rotate Left Quadword then AND with Mask (Implemented in 4e272668)
• vs[lr]q: Vector Integer Shift Left/Right Instructions (Implemented in 3e39edb6 and 946c3491)
• vmul[eo][su]d: Vector Multiply Even/Odd Signed/Unsined Doubleword (Implemented in 80eca687)
• vmulh[su][wd]: Vector Multiply High Signed/Unsigned Word/Doubleword (Implemented in 29e9dfcf)
• vdiv[e][su][wdq]: Vector Divide (Extended) Signed/Unsigned Word/Doubleword/Quadword
• vmod[su][wdq]: Vector Modulo Signed/Unsigned Word/Doubleword/Quadword
• vgnb: Vector Gather every Nth Bit (Implemented in f622ebe7)
• vstri[bh][lr]: Vector String Isolate Byte/Halfword Left/Right-justified (Implemented in fb5303cc)
• vclr[lr]b: Vector Clear Left/Rightmost Bytes (Implemented in 08d512e1 and fb1b5675)
• vmsumcud: Vector Multiply-Sum & write Carry-out Unsigned Doubleword (Implemented in 5476ef1d)

And following VSX instructions:

• lxv[lr][bhwd]x: Load VSX Vector Rightmost Byte/Halfword/Word/Doubleword (Implemented in 604d00c7)
• stxv[lr][bhwd]x: Store VSX Vector Rightmost Byte/Halfword/Word/Doubleword (Implemented in 604d00c7)
• xxm[tf]acc: VSX Move to/from Accumulator
• xxsetaccz: VSX Set Accumulator to Zero
• xxpermx: VSX Vector Permute Extended (Implemented in 41c2877f)
• xxeval: VSX Vector Evaluate (Implemented in 1015fcab)
• xvi{4,8,16}ger[s][pp]: VSX Vector {4,8,16}-bit Signed/Unsigned Integer GER rank-{8,4,2} update (Positive multiply, Positive accumulate)
• xvf{16,32,64}ger[pn][pn]: VSX Vector {16,32,64}-bits Floating-Point GER rank-{2,1,1} update (Positive/Negative multiply, Positive/Negative accumulate)
• xvbf16ger[pn][pn]: VSX Vector bfloat16 GET rank-2 update (Positive/Negative multiply, Positive/Negative accumulate)
• xxgenpcv[bhwd]m: VSX Vector Generate PCV from Byte/Halfword/Word/Doubleword Mask (Implemented in b090f4f1)
• xvtlsbb: VSX Vector Test Least-Significant Bit by Byte (Implemented in d518239b)
• xscmp{eq,ge,gt}qp: VSX Scalar Compare Greater Than/Equal Quad-Precision (Implemented in 568e7c4d)
• xs{max,min}cqp: VSX Scalar Maximum/Minimum Type-C Quad-Precision (Implemented in 7b8d6e3e)
• xscvqp[su]qz: VSX Vector Convert Quad-Precision to Signed/Unsigned Quadword (Implemented in b3d45205)
• xscv[su]qqp: VSX Vector Convert Signed/Unsigned Quadword to Quad-Precision (Implemented in 67332e07)
• xvcvbf16sp: VSX Vector Convert bfloat16 to Single-Precision format (Implemented in 3909ff1f)
• xvcvspbf16: VSX Vector Convert with round Single-Precision to bfloat16 format (Implemented in 3909ff1f)

Additional information

PowerISA_public.v3.1.pdf