QEMU registers support on x64
Goal
There are two issues to address.
Issue #1:
Support in adding the missing x86-64 system registers to the QEMU x86-64 GDb server.
Issue #2: Support in adding MSR registers to the QEMU-x86-64 GDb servers - so that the registers can be accessible via GDB query register command "p").
These registers are needed to successfully debug kernel and pre-kernel system applications for different Operating Systems. This also allows for a user to see same register information populated like they would if doing a QEMU ARM64 GBD server.
Technical details
For Issue #1 - Example list of missing x86-64 system registers for the QEMU x86-64 GDB server:
DWORD64 IDTBase;
DWORD64 IDTLimit;
DWORD64 GDTBase;
DWORD64 GDTLimit;
DWORD SelLDT;
SEG64_DESC_INFO SegLDT;
DWORD SelTSS;
SEG64_DESC_INFO SegTSS;
SEG64_DESC_INFO DescriptorCs;
SEG64_DESC_INFO DescriptorSs;
SEG64_DESC_INFO DescriptorGs;
SEG64_DESC_INFO DescriptorFs;
SEG64_DESC_INFO DescriptorEs;
SEG64_DESC_INFO DescriptorDs;
where struct _SEG64_DESC_INFO
{
DWORD64 SegBase;
DWORD64 SegLimit;
DWORD SegFlags;
} SEG64_DESC_INFO;
For Issue #2 - Here are the list of most relevant MSRs:
#define MSR_TSC 0x10
#define MSR_IA32_TSC_ADJUST 0x3B
#define MSR_BIOS_UPDT_TRIG 0x79
#define MSR_BIOS_SIGN 0x8B
#define MSR_SYSENTER_CS 0x00000174
#define MSR_SYSENTER_ESP 0x00000175
#define MSR_SYSENTER_EIP 0x00000176
#define MSR_PAT 0x277
#define MSR_MCG_CAP 0x179
#define MSR_MCG_STATUS 0x17a
#define MSR_MCG_CTL 0x17b
#define MSR_MC0_CTL 0x400
#define MSR_MC0_STATUS 0x401
#define MSR_MC0_ADDR 0x402
#define MSR_MC0_MISC 0x403
#define MSR_MC0_CTL2 0x280
#define MSR_EFER 0xc0000080
#define MSR_STAR 0xc0000081
#define MSR_LSTAR 0xc0000082
#define MSR_CSTAR 0xc0000083
#define MSR_SYSCALL_MASK 0xc0000084
#define MSR_FS_BASE 0xc0000100
#define MSR_GS_BASE 0xc0000101
#define MSR_GS_SWAP 0xc0000102
Edited by Christopher