Tricore: missing a few TC1.6.2 instruction set

I found some new instructions added to Tricore TC1.6.2, But QEMU lacks the translation of these instructions.

• POPCNT.W
• CRCN
• LHA
• CRC32.B
• CRC32L.W
• FTOHP
• HPTOF
• SHUFFLE

@kbastian-qemu : FYI

added target: tricore label

added workflowTriaged label

Thanks for reporting these. I have a branch that implements

• POPCNT.W
• LHA
• CRC32.B
• CRC32L.W
• SHUFFLE

Will send patches as soon as I have tested them.

mentioned in commit dc0b4368

mentioned in commit 0eaafe33

mentioned in commit 73f874d9

mentioned in commit 4e3377bb

mentioned in commit fd6f446a

To summarize, only left unimplemented are:

• CRCN
• FTOHP
• HPTOF

@kbastian-qemu sorry for being an annoyance, but regarding floating points - do you plan to implement those? As we use QEMU as part of the rz-tracetest solution it is important for us to check uplifting of TriCore to RzIL against emulation:

• https://github.com/rizinorg/rz-tracetest/issues/10
• https://github.com/BinaryAnalysisPlatform/qemu/issues/23
• https://github.com/rizinorg/rizin/pull/3478
• https://github.com/rizinorg/rizin/issues/3529
• https://github.com/rizinorg/rizin/issues/2080

Right now, I'm working on CRCN, but it is not correct yet. I started implementing the floating point insns as well, but they are also tricky to emulate correctly. If you want to validate insns, try using TSIM from Infineon. This is the golden simulator used to verify HW. You can get it bundled with the free entry toolchain.

added workflowPatch available label and removed workflowTriaged label

Hi, I came around implementing the remaining instructions. See the patch.

mentioned in commit 3e2a5107

mentioned in commit 815061b9

mentioned in commit 5e0e06d9

closed with commit 5e0e06d9