riscv: reset_vec uses CSR even when disabled causing inability to boot

Host environment

• Operating system: N/A
• OS/kernel version: N/A
• Architecture: N/A
• QEMU flavor: qemu-system-riscv*
• QEMU version: used: 7.2.50
• QEMU command line:

  ./qemu-system-riscv32 -cpu rv32,d=off,f=off,Zicsr=off

Description of the problem

By running QEMU with the CSR instructions turned off the QEMU reset vector @0x1000 will call a CSR instruction causing a halt.

hw/riscv/boot.c:riscv_setup_rom_reset_vec:307

    /* reset vector */
    uint32_t reset_vec[10] = {
        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
        0x02828613,                  /*     addi   a2, t0, %pcrel_lo(1b) */
        0xf1402573,                  /*     csrr   a0, mhartid  */
        0,
        0,
        0x00028067,                  /*     jr     t0 */
        start_addr,                  /* start: .dword */
        start_addr_hi32,
        fdt_load_addr,               /* fdt_laddr: .dword */
        fdt_load_addr_hi32,
                                     /* fw_dyn: */
    };

Steps to reproduce

1. Run any rv32 binary with ./qemu-system-riscv32 -cpu rv32,d=off,f=off,Zicsr=off

To view using GDB use ./qemu-system-riscv32 -cpu rv32,d=off,f=off,Zicsr=off -S -s gdb-multiarch --ex="target remote localhost:1234" -ex "layout asm" then type si till $pc jumps to zero on csrr a0, mhartid