Tags

Tags give the ability to mark specific points in history as being important
  • v3.1.1

    bb29521c · update CHANGELOG ·
    3.1.1 - 2025-02-03
    ==================
    Fixed
    -----
    - sw: fix crash on missing HTVIC instance during FPGA devices initialization.
  • v3.1.0

    3.1.0 - 2023-10-17
    ==================
    
    Added
    -----
    - svec-flasher can export bash-like output to be used in udev
    - svec-flasher accepts the format VME.<slotnumber> as input
    
    Changed
    -------
    - [ci] general improvements
    - [bld] improved Makefiles
    
    Fixed
    -----
    - svec-flasher bugfixes
  • v3.0.0

    3.0.0 - 2022-12-05
    ==================
    Added
    -----
    - ci: better automation
    - sw: support for Linux 5.10
    
    Removed
    -------
    - hdl: unused and obsolete top-levels and simulations
    - hdl: Xilinx chipscope for SFPGA (files were actually for AFPGA)
    
    Changed
    -------
    - hdl: 'golden_wr' top-level renamed to 'wr_example'
    - hdl: 'template' testbench now used for simulating the golden top-level
    - sw|API change: the API to flash a bitstream moved from debugfs to sysfs. The
      Linux kernel community removed API we used. The same behavior was achievable
      only using sysfs.
    - bld: improved Makefiles
    
    Fixed
    -----
    - hdl: building of all top-levels
    - hdl: missing ddr and wr-cores dependencies
    - hdl: corrected and re-enabled timing constraints
    - hdl: location of general-cores in rtl Manifest
  • v2.0.4

    2.0.4 - 2021-07-29
    ==================
    Fixed
    -----
    - sw: improve compatibility with newer ( > 3.10) Linux kernel version
  • v2.0.3

    2.0.3 - 2021-03-22
    ==================
    Fixed
    -----
    - sw: fix SVEC flasher size
  • v2.0.2

    2.0.2 - 2021-03-16
    ==================
    Changed
    -------
    - sw: better version validation implementation
  • v2.0.1

    2.0.1 - 2021-02-08
    ==================
    Added
    -----
    - sw: dynamically set the compatibility version between software and
    FPGA
    - sw: added the possibility to ignore the version check
    
    Changed
    -------
    - hdl: the DMA interface changed to support BLT and MBLT acquisitions
  • v1.5.2

    1.5.2 - 2020-11-24
    ==================
    Added
    -----
    - sw: tool to inspect SVEC bitstream ROM
    
    Fixed
    -----
    - hdl: svec-base version
  • v1.5.1

    1.5.1 - 2020-11-24
    ==================
    Fixed
    -----
    - sw: NULL pointer at load time when using the SPI controller
    - sw: remove old unload procedure that causes BUG_ON to be triggered
      without valid reasons
  • v1.5.0

    1.5.0 - 2020-11-02
    ===================
    Added
    -----
    - sw: add SPI flash partitions
    - hdl: enable DDR4
    
    Changed
    -------
    - sw: internal driver improvements
  • v1.4.12

    [1.4.12] 2020-06-03
    ===================
    Added
    -----
    - [hdl] ignore autogenerated files to build metadata (otherwise the
      repository is always marked as dirty)
    
    Fixed
    -----
    - [sw] impossibility of loading application because of wrong address
      space
  • v1.4.11

    [1.4.11] 2020-05-20
    ===================
    Added
    -----
    - [hdl] export DDMTD clock output
  • v1.4.10

    [1.4.10] 2020-05-12
    ==================
    Added
    -----
    - [hdl] metadata source-id automatic assignment
    - [hdl] add option to consider AM in VME slave decoder
    
    Fixed
    -----
    - [hdl] fix typos when ddr is not configured. This froze the board when
      reading a ddr data register.
    
    Changed
    -------
    - [sw] Linux device hierarchy seen in sysfs. It is incompatible but
      tools, today do not rely in this. So we take the freedom to change
      it without a major release.
    - [sw] on device removal the IRQ vector number in the CR/CSR space is set
      to 0x0
  • v1.4.9

    [1.4.9] 2020-03-10
    ==================
    Fixed
    -----
    - [sw] reduce allocation on stack
    - [sw] automatically remove device after FPGA reprogram (otherwise unusable)
  • v1.4.8

    [1.4.8] 2020-02-12
    ==================
    Fixed
    -----
    - [sw] fix kernel crash when programming new bitstream
  • v1.4.7

    [1.4.7] 2020-01-15
    ============
    Added
    -----
    - [hdl] Add support for DDR5 bank to SVEC base
    
    Fixed
    -----
    - [hdl] DDR constraints
    - [hdl] DDR controller generic values are now properly capitalised
    - [sw] Update svec-flasher to work with new type of flash memory used in newer SVEC boards
  • v1.4.6

    [1.4.5] 2019-12-16
    ==================
    Changed
    -----
    - [sw] better integration in coht, rename environment variable to FPGA_MGR
  • v1.4.5

    [1.4.5] 2019-12-16
    ==================
    Fixed
    -----
    - [sw] suggested fixed reported by checkpatch and coccicheck
  • v1.4.4

    [1.4.4] 2019-12-13
    ==================
    Fixed
    -----
    - [sw] soft dependency from i2c_ohwr to i2c-ocores
  • v1.4.3

    [1.4.3] 2019-10-17
    ==================
    Added
    -----
    - [doc] sphinx documentation