Tags give the ability to mark specific points in history as being important
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v3.0.5
ef1852f6 · ·3.0.5 - 2025-09-04 ================== Added ----- - sw: Debian package - hdl: configurable gennum FIFO size Fixed ----- - sw: make driver compatible with Linux up to version 6.12
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v3.0.4
77d0e6d3 · ·3.0.4 - 2024-12-17 ================== Fixed ----- - sw: fix crash on missing HTVIC instance during FPGA devices initialization.
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v3.0.3
e7526e61 · ·3.0.3 - 2024-04-17 ================== Fixed ----- - sw: use IRQF_ONESHOT to avoid bursts of interrupts on recent kernels
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v3.0.2
ce9ba31d · ·3.0.2 - 2024-03-22 ================== Fixed ----- - sw: implement a timeout mechanism to wait for DDR Calibration
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v3.0.1
e4987acf · ·3.0.1 - 2023-10-19 ================== Changed ------- - ci: general improvements - bld: improved Makefiles - hdl: automate version generation for metadata
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v3.0.0
affb718e · ·3.0.0 - 2022-11-16 ================== Added ----- - ci: better automation - sw: support for Linux 5.10 Changed ------- - sw|API change: the API to flash a bitstream moved from debugfs to sysfs to keep it symmetric to the SVEC driver that needed to change due to an incompatibility in 5.10 - hdl: update gn4124 and ddr3 ip-cores - dist: improved RPM packaging - bld: improved Makefiles Fixed ----- - sw: prevent kernel crash on invalid DMA transfer pointer - sw: prevent objtool warning about frame pointer state mismatch - doc: fixed building and configuration files to avoid warning on sphinx 5.x
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v2.1.6
483c3fc7 · ·2.1.6 - 2021-07-29 ================== Fixed ----- - sw: improve compatibilty with newer (greater than 3.10) Linux kernel version
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v2.1.5
fffa8b42 · ·2.1.5 - 2021-05-18 ================== Fixed ----- - sw: check if FPGA is programmed before loading FPGA devices - doc: improve documentation
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v2.1.4
fd485c8b · ·2.1.4 - 2020-11-23 ================== Fixed ----- - sw: SPEC driver detects the correct FLASH only on drivers reload
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v2.1.3
c3ffa27d · ·2.1.3 - 2020-11-16 ================== Added ----- - sw,drv: module parameter to ignore bitstream version check (for development or debug) - sw: the spec-firmware-version tool can dump build-info Fixed ----- - hdl: DMA failures fixed with thight timing constraints
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v2.1.2
bccad6f3 · ·2.1.2 - 2020-11-09 ================== Fixed ----- - sw: automatize version validation
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v2.1.1
a0f9a0b3 · ·2.1.1 - 2020-11-09 ================== Fixed ----- - hdl: report the correct version in spec-golden design
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v2.1.0
061bbd7e · ·2.1.0 - 2020-11-09 ================== Fixed ----- - hdl: cross-page DMA failure - sw: DMA pool memory leak - sw: fix concurrent DMA tasklet Changed ------- - tst: keep the DMA interface open while testing to avoid continuos memory re-allocation Added ----- - sw: tool to firmware version inspection - sw: FLASH partitions
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v2.0.2
26b16bd3 · ·2.0.2 - 2020-09-29 ================== Fixed ----- - hdl: L2P DMA issues reported with slower hosts
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v2.0.1
f63c5572 · ·2.0.0 - 2020-08-20 ================== Fixed ----- - program 2 or more SPEC FPGAs in parallel. There is a bug in the GN412x chip that we fixed in software by serializing any attempt of parallel programming -
v2.0.0
1e9e50ec · ·2.0.0 - 2020-07-30 ================== Added ----- - hdl: new testbench to test the DMA feature (read/write to DDR memory) in the new golden. - sw: basic Python module to handle DMA and FPGA programming - sw: user-space DMA interface in debugfs (read/write) - tst: add integration tests for DMA transfers Changed ------- - hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers. - hdl: Cleanup of top-levels, addition of DMA to the golden. Fixed ----- - hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by inadequate flow control. - hdl: typo in synthesis constraints. -
v1.4.15
8c641a3b · ·[1.4.15] 2020-06-03 =================== Added ---- - [hdl] ignore autogenerated files to build metadata (otherwise the repository is always marked as dirty)
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v1.4.14
cd98b268 · ·[1.4.14] 2020-05-28 =================== Added ----- - [hdl] export DDMTD clock output
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v1.4.13
28b1a2cc · ·[1.4.13]·2020-05-12 =================== Fixed ----- -·[hdl]·report·correct·version·in·spec-base·metadata
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v1.4.12
d70eafc6 · ·[1.4.12] 2020-05-12 =================== Added ----- - [hdl] metadata source-id automatic assignment Changed ----- - [sw] do not double remap memory