Commits · master · Michael Tokarev / QEMU · GitLab

Snippets Groups Projects

Jan 19, 2025
- Merge tag 'pull-riscv-to-apply-20250119-1' of https://github.com/alistair23/qemu into staging · d6430c17
  Stefan Hajnoczi authored 2 months ago
  d6430c17
Jan 18, 2025
- hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events · f04cac4f
  Philippe Mathieu-Daudé authored 2 months ago
  f04cac4f
- target/riscv: Support Supm and Sspm as part of Zjpm v1.0 · 941f76e2
  Alexey Baturo authored 2 months ago
  941f76e2
- hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache · fa622855
  Jason Chien authored 4 months ago
  fa622855
- target/riscv: Add Smdbltrp ISA extension enable switch · 2d8e8259
  Clément Léger authored 2 months ago
  2d8e8259
- target/riscv: Implement Smdbltrp behavior · 00af7d53
  Clément Léger authored 2 months ago
  00af7d53
- target/riscv: Implement Smdbltrp sret, mret and mnret behavior · f2efb6e7
  Clément Léger authored 2 months ago
  f2efb6e7
- target/riscv: Add Smdbltrp CSRs handling · d2e92f1c
  Clément Léger authored 2 months ago
  d2e92f1c
- target/riscv: Add Ssdbltrp ISA extension enable switch · b0edcbe7
  Clément Léger authored 2 months ago
  b0edcbe7
- target/riscv: Implement Ssdbltrp exception handling · 967760f6
  Clément Léger authored 2 months ago
  967760f6
- target/riscv: Implement Ssdbltrp sret, mret and mnret behavior · 72d71d87
  Clément Léger authored 2 months ago
  72d71d87
- target/riscv: Add Ssdbltrp CSRs handling · 0aadf816
  Clément Léger authored 2 months ago
  0aadf816
- target/riscv: Fix henvcfg potentially containing stale bits · 507957eb
  Clément Léger authored 2 months ago
  507957eb
- target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg · fdb7bce4
  Atish Patra authored 2 months ago
  fdb7bce4
- target/riscv: Add implied rule for counter delegation extensions · 2a754d69
  Atish Patra authored 2 months ago
  2a754d69
- target/riscv: Invoke pmu init after feature enable · 04ff272d
  Atish Patra authored 2 months ago
  04ff272d
- target/riscv: Add counter delegation/configuration support · 6247dc2e
  Kaiwen Xue authored 2 months ago
  6247dc2e
- target/riscv: Add select value range check for counter delegation · b6504cd0
  Kaiwen Xue authored 2 months ago
  b6504cd0
- target/riscv: Add counter delegation definitions · e84af935
  Kaiwen Xue authored 2 months ago
  e84af935
- target/riscv: Add properties for counter delegation ISA extensions · f2548886
  Atish Patra authored 2 months ago
  f2548886
- target/riscv: Support generic CSR indirect access · 5e33a208
  Kaiwen Xue authored 2 months ago
  5e33a208
- target/riscv: Enable S*stateen bits for AIA · dbcb6e1c
  Atish Patra authored 2 months ago
  dbcb6e1c
- target/riscv: Decouple AIA processing from xiselect and xireg · dc028072
  Kaiwen Xue authored 2 months ago
  dc028072
- target/riscv: Add properties for Indirect CSR Access extension · 51c4f3e9
  Kaiwen Xue authored 2 months ago
  51c4f3e9
- hw/riscv/virt: Remove unnecessary use of &first_cpu · cb938a0a
  Philippe Mathieu-Daudé authored 2 months ago
  cb938a0a
- target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu · 7703a1d1
  Philippe Mathieu-Daudé authored 2 months ago
  7703a1d1
- target/riscv: Add Zicfilp support for Smrnmi · 0266fd8b
  Frank Chang authored 2 months ago
  0266fd8b
- target/riscv: Add Smrnmi cpu extension · f9653d4e
  Tommy Wu authored 2 months ago
  f9653d4e
- target/riscv: Add Smrnmi mnret instruction · 3157a553
  Tommy Wu authored 2 months ago
  3157a553
- target/riscv: Handle Smrnmi interrupt and exception · c1149f69
  Tommy Wu authored 2 months ago
  c1149f69
- target/riscv: Add Smrnmi CSRs · 5db557f8
  Tommy Wu authored 2 months ago
  5db557f8
- target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig · 36de64b7
  Tommy Wu authored 2 months ago
  36de64b7
- target/riscv: Enable updates for pointer masking variables and thus enable... · e00e2749
  Alexey Baturo authored 2 months ago
  e00e2749
- target/riscv: Apply pointer masking for virtualized memory accesses · 4d160093
  Alexey Baturo authored 2 months ago
  4d160093
- target/riscv: Update address modify functions to take into account pointer masking · 4d501a7a
  Alexey Baturo authored 2 months ago
  4d501a7a
- target/riscv: Add pointer masking tb flags · 6ec718e3
  Alexey Baturo authored 2 months ago
  6ec718e3
- target/riscv: Add helper functions to calculate current number of masked bits for pointer masking · 3d1c5c08
  Alexey Baturo authored 2 months ago
  3d1c5c08
- target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 · 33ca99a1
  Alexey Baturo authored 2 months ago
  33ca99a1
- target/riscv: Remove obsolete pointer masking extension code. · 37089cb8
  Alexey Baturo authored 2 months ago
  37089cb8
- target/riscv: add trace in riscv_raise_exception() · 8f1a1289
  Daniel Henrique Barboza authored 2 months ago
  8f1a1289