pinctrl: mediatek: common: add quirk for broken set/clr modes
On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Add a quirk for such SoCs, so that instead of using the SET/CLR register use the main R/W register to read/update/write the modes.
Signed-off-by: Fabien Parent fparent@baylibre.com