Add rule that components shouldn't put silkscreen outside the board edges (!36) · Merge requests · KiCad / KiCad Libraries / KiCad Library Conventions

John Beard requested to merge johnbeard/klc:silk-edges into master Jul 15, 2023

Many connectors are allowed to overhang - if they include a full silkscreen outline, this is a DRC error in Kicad 7.

Instead, they should pull the silkscreen back from possible board edges.

0.5mm chosen as a clearance because this should keep clear even of v-scored edge processes.

I'm not particularly attached to 0.5mm as a number, I imagine most fabs not using v-scores will get quite a bit closer, but seems like that's probably close enough for general purposes?

Example image used:

Edited Jul 16, 2023 by John Beard

Add rule that components shouldn't put silkscreen outside the board edges

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