Scripted qfn-56-1ep used for cypress mcu (replaces #400)

Originally submitted in #400.

datasheet used for getting the sizes are:

• http://www.ti.com/lit/an/scea032/scea032.pdf (From 2003 so i did not use the recommended footprint from there as it is now outdated.)
• http://www.cypress.com/file/138911/download (Has the same sized part but with slightly smaller tolerances on nearly every measurement. I used the TI measurements as this was used in the original PR. I can easily change it to use the cypress measurements)

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Symbol that uses this has been merged in https://github.com/KiCad/kicad-symbols/pull/289

A very strange footprint with top tented vias does also exist. But that one is not connected to the symbol. (I researched this a lot. It seems there is no real consensus what the optimal solution is for avoiding solder wicking. It seems right now the solution most used is to simply increase solder paste coverage to make up for the fact that some of it is lost inside the vias. In addition to using very small vias. Bottom tenting what we normally use is also here to help out even more.)

This footprint is independent of the decision which footprint should be connected to that cypress part.

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Generator parameters:

QFN-56-1EP_8x8mm_P0.5mm_EP4.8x5.5mm:
  device_type: 'QFN'
  size_source: 'http://www.ti.com/lit/an/scea032/scea032.pdf (page 4)'
  ipc_class: 'qfn' # 'qfn_pull_back'
  body_size_x:
    nominal: 8
    tolerance: 0.15
  body_size_y:
    nominal: 8
    tolerance: 0.15
  lead_width:
    nominal: 0.23
    tolerance: [0.05, 0.07]
  lead_len_min: 0.3
  lead_len_max: 0.5

  EP_size_x_min: 4.35
  EP_size_x_max: 4.65
  EP_size_y_min: 5.05
  EP_size_y_max: 5.35
  EP_num_paste_pads: [4, 4]

  thermal_vias:
    count: [5, 5]
    drill: 0.2
    paste_via_clearance: 0.1
    EP_paste_coverage: 0.6

  pitch: 0.5
  num_pins_x: 14
  num_pins_y: 14