ERC checks handle connections between a common sub-circuit

ERC checks handle connections between a common sub-circuit in a heirarchical schematic

Fixes #10926 (closed)

Contains the following changes:

• Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic comparison between items causing ERC violations (e.g. pins) when associated with a SCH_SHEET_PATH context.
• Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items which caused an ERC violation. This allows correct display of markers on the sheets of interest only, and allows correct naming resolution and cross-probing from the ERC dialog.
• Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly resolves component references across heirarchical sheets using the associated SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed correctly in the ERC results tree.
• Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing an ERC violation.
• Increments the schematic file version.
• When loading a schematic with legacy ERC exclusions, discards those of type ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the information which is now stored with these exclusions (sheet paths for error location and related items). Requiring users to (once) re-add exclusions is preferable to silently incorrectly matching new ERC issues to legacy exclusions.