Cadence Allegro PCB Designer netlist output
Due to the way my team collaborates with vendors, we have been using eeschema for schematic capture, but exporting the netlist to a Cadence Allegro PCB Designer-compatible format for our PCB engineers to ingest.
We currently have a ~100 line python3 script that uses the kicad_netlist_reader module and is added to eeschema as an external netlister, which has been working well. It looks like all the other built-in exporters are written in C++.
Would this exporter be of interest to the KiCAD project? Would you want it rewritten in C++?