Add Chained Topological Constraint (prevent branching/loops in a net)
Description
This is a feature request for adding what is termed "Chained Topology constraint" in other EDA software. The idea is that some types of nets might require that the route should be a straight sequence of track segments without any additional stubs or loops.
Steps to reproduce
N/A
KiCad Version
Application: KiCad PCB Editor (64-bit)
Version: (5.99.0-10480-g6b9e44e59c), release build
Libraries:
wxWidgets 3.1.4
libcurl/7.74.0-DEV Schannel zlib/1.2.11
Platform: Windows 10 (build 19041), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
Date: May 2 2021 09:02:14
wxWidgets: 3.1.4 (wchar_t,STL containers)
Boost: 1.75.0
OCC: 7.5.0
Curl: 7.74.0-DEV
ngspice: 34
Compiler: Visual C++ 1928 without C++ ABI
Build settings:
KICAD_SCRIPTING=ON
KICAD_SCRIPTING_MODULES=ON
KICAD_SCRIPTING_PYTHON3=ON
KICAD_SCRIPTING_WXPYTHON=ON
KICAD_SCRIPTING_WXPYTHON_PHOENIX=ON
KICAD_SCRIPTING_ACTION_MENU=ON
KICAD_USE_OCC=ON
KICAD_SPICE=ON