PCB-first (or mixed) workflow for layout-driven design
Description
This feature would increase the amount of flexibility in design, enabling the user to start by designing a key part of the board layout, then assign symbols and generate the equivalent of a netlist in pcbnew and load it into eeschema, resulting in a ratsnest in eeschema.
Example workflow for making a LED clock:
- Create a circular array of LEDs and resistors that looks good
- Assign symbols to footprints, then generate (netlist?)
- Open eeschema and load (netlist?), resulting in a ratsnest in eeschema
- (Continue as normal)
It would be extremely helpful for designing boards such as LED signs, clocks and hacker badges, as well as things like placing extra capacitors wherever you see fit, and reverse-engineering.
I believe that that the ability to relax the traditional workflow would be a milestone from a usability perspective, while simultaneously flattening the learning curve.
Also, I suppose that it might be a missing piece for cleanly implementing functions such as "Pcbnew: allow to increment module refdes in arrays (lp:#1819142)".