zone fill clearance does not respect custom DRC rule : enclosedByArea
Description
- The "enclosedByArea" does not seem to be symmetrical, and leads to incorrect fills ( clearance between net A and B is not the same when filling A or B )
See a compressed project:
Steps to reproduce
- Create a custome like : ( clearance constraint except if the elements are in a zone called 'PD1'
(rule "Iso"(constraint clearance (min 2mm))(condition "(A.NetClass == 'P1') && ( B.NetClass == '50VINT' ) && ( ! A.enclosedByArea('PD1') ) && ( ! B.enclosedByArea('PD1') ) "))
Here is the expected result:
KiCad Version
Application: KiCad PCB Editor x64 on x64
Version: 8.0.3, release build
Libraries:
wxWidgets 3.2.4
FreeType 2.12.1
HarfBuzz 8.3.0
FontConfig 2.14.2
libcurl/8.5.0-DEV Schannel zlib/1.3
Platform: Windows 10 (version 19045), édition 64-bit, 64 bit, Little endian, wxMSW
OpenGL: Intel, Intel(R) UHD Graphics, 4.6.0 - Build 30.0.101.1122
Build Info:
Date: Jun 3 2024 19:04:47
wxWidgets: 3.2.4 (wchar_t,wx containers)
Boost: 1.83.0
OCC: 7.8.1
Curl: 8.5.0-DEV
ngspice: 42
Compiler: Visual C++ 1939 without C++ ABI
Build settings: