DRC castellated PTH pads on "edge.cuts" slot and "NPTH" slot behave differently

Description

I would like to know what is the difference between an NPTH with no copper layers and a slot made using the "edge.cuts" layer. From my point of view, the only difference is that the NPTH has the inside area filled up, while the "edge.cuts" does not.

In the image below I present the problem. I have a vertical daughterboard that mates through a slot. For this reason, I made castellated pads for soldering the daughterboard to the main board. The footprint on the far left is practically the same as the footprint on the far right, the only difference being one is made with an NPTH and the other with the edge.cuts layer using lines and arcs.

Trying to route on the left footprint gives DRC violation error.

Trying to route on the right footprints has no DRC violation errors whatsoever.

Is this a bug or a feature? I tried to look into PNS router and half-castellation (lp:#1806740) (#1790 - closed) to no avail. It seems to be a missing DRC check for NPTH slots.

Steps to reproduce

1. Open this project on 7.99 nightly

   DRC_edge_cuts_castellated_test.zip

2. Open PCBNew.

3. Try to make wire connections between the pad 1 and of the EDGE_CUTS and NPTH footprint.

4. You will not be able to make a wire from the NPTH due to the DRC violation error.

KiCad Version

Application: KiCad PCB Editor x64 on x64

Version: 7.99.0-3781-gc93eb679c1, release build

Libraries:
	wxWidgets 3.2.4
	FreeType 2.12.1
	HarfBuzz 8.2.1
	FontConfig 2.14.2

Platform: Windows 11 (build 22631), 64-bit edition, 64 bit, Little endian, wxMSW

	wxWidgets: 3.2.4 (wchar_t,wx containers)
	Boost: 1.83.0
	OCC: 7.7.1
	Curl: 8.4.0-DEV
	ngspice: 41
	Compiler: Visual C++ 1936 without C++ ABI

Build settings: