PcbNew 6.99: Castellated holes throw a board edge violation in DRC, which they shouldn't
Description
Currently castellated holes have merely a flag for Gerber output. They should be treated appropriately in DRC (board edge violations, minimum spoke count? )
Steps to reproduce
- on a board with castellated holes, run a DRC
KiCad Version
Application: KiCad PCB Editor (64-bit)
Version: (6.99.0-1053-g8ef4ef8d96), release build
Libraries:
wxWidgets 3.1.5
FreeType 2.11.1
libcurl/7.78.0-DEV Schannel zlib/1.2.11
Platform: Windows 10 (build 22000), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
Date: Feb 24 2022 19:16:55
wxWidgets: 3.1.5 (wchar_t,wx containers)
Boost: 1.76.0
OCC: 7.6.0
Curl: 7.78.0-DEV
ngspice: 36
Compiler: Visual C++ 1928 without C++ ABI
Build settings:
KICAD_USE_OCC=ON
KICAD_SPICE=ON
Edited by Martin Straub