pci-bridge/cxl_upstream: Implement lock register.

When the lock is set, certain config space registers become
read only.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

hw/pci-bridge/cxl_upstream.c

@@ -73,6 +73,24 @@ static void cxl_usp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
             }
         }
     }
+    if (range_contains(&usp->cxl_cstate.dvsecs[PCIE_CXL_DEVICE_DVSEC], addr)) {
+        uint16_t offset = usp->cxl_cstate.dvsecs[PCIE_CXL_DEVICE_DVSEC].lob;
+
+        addr -= offset;
+        if (addr == offsetof(CXLDVSECDevice, lock)) {
+            if (val & 0x1) {
+                /*
+                 * If lock is set, change write masks to prevent updates to
+                 * locked registers in config space.
+                 */
+                dev->wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0;
+                dev->wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0;
+                dev->wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo)] = 0;
+                dev->wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0;
+                dev->wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo)] = 0;
+            }
+        }
+    }
 }
 
 static void cxl_usp_write_config(PCIDevice *d, uint32_t address,