qspi design revamp plan
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define memory mapped registers -
use DCBus module interface to be bus protocol agnostic -
optimize and cleanup the phase_change functions -
cleanup clock generation mechanism - right now we use a clock divider to identify edges (pos/neg). Is there a better way ? -
clean up fsm for 1S-1S-1S, 2S-2S-2S, 4S-4S-4S -
clean up fsm 1D-1D-1D, 2D-2D-2D, 4D-4D-4D -
clean up interrupt handling and abort routines.