This project consists in a small version of a Digital Pulse Processor for the smr765 school.
There are two groups of files, one for an ideal pulse processor (square signals) and the other for typical signals coming from a Electromagnetic Calorimeter (ECAL) scintillator signal model.
## DPP for square ideal pulses
For the first part of the project the main idea is to have a minimal version of a DPP capable of
measure the amplitude of square ideal pulses.
All the required files are in the folder **dpp_0**. The synthesizable files are under **dpp_0/src** and the
simulation files under **dpp_0/simul**. The files for the SDK are under **dpp_0/sdk**
## DPP for ECAL like pulses
For the second part of the project the participants will have to implement an upgraded version of a DPP capable of
measure the amplitude of pulses synthesized with a script for the ECAL2 COMPASS model.
All the required files are in the folder **dpp_1**. The synthesizable files are under **dpp_1/src**, the
simulation files under **dpp_1/simul** and the python script under **dpp_1/soft**.
1. Clone the [easy_dpp](https://gitlab.com/ictp-mlab/easy_dpp) repository in the computer where you will build your project. Do not forget the `--recursive` flag.
4. Build the block design following the specific instructions for each case.
5. Create HDL wrapper in the block design and set it as **Top**.
6. Follow all the steps to **Generate Bitstream**.
7. While you wait for the bitsteram to generate use this time to understand the block design. Notice how the **COMBLOCK** registers controls the circuit. Notice also how the Input and Output FIFOs are connected to the DPP. These information will be usefull for the DPP configuration.
8. Export the Hardware (include the bitstream).
9. Launch **Vitis**.
### Vitis Project
1. Create a new **empty application project** in **Standalone** configuration calling it `DPP_XX` where `XX` corresponds to case `0` or `1`.
2. Import the **C** code available in `<easy_dpp_git_path>/dpp_x/sdk` sources into your Vitis project.
3. Build the project and run it in the FPGA.
# Digital Pulse Processor, Light version 0
This first version of the DPP is for processing ideal square pulses,
the IP takes a stream of data from a FIFO (Comblock FIFO Out),
detects the arrival of a pulse with a first order derivative
when its value (derivative) esceeds a threshold values defined
by the user in runtime and, stores the amplitude value in another
FIFO (Comblock In) to be read afterwards.
The DPP_0 block have the following Ports:
| Port | Type | Definition |
| ---- | ---- | ---------- |
| clk_i | Input | Clock Input |
| rst_i | Input | Reset Input |
| ena_i | Input | DPP_0 Enable signal |
| ADC_data_i | Input | Data Input |
| threshold_high_i | Input | Detection Threshold value |
| op_mode_i | Input | Operation Mode* |
| data_o | Output | Data Output |
| fir_wr_en_mux_out | Output | FIFO Write Enable/ Data Valid|
The four operation modes are the following:
| Operation Mode | Description |
| -------------- | ----------- |
| "00" | Amplitude acquisition |
| "01" | Input signal |
| "10" | Long FIR continuous output (NI*) |
| "11" | Derivative FIR continuous output (NI*) |
## DPP_0 Procedure
### Prepare the Project
1. Generate the project in Vivado for the Zedboard using the information given in the previous section.
2. Create a Block Design
3. Include the Processing System
4. Include the COMBLOCK IP Core
Select the following configuration options for the COMBLOCK
2. In the **"Project Manager"** make click on `Run Simulation -> Run Behavioral Simulation`.
3. Run the Simulation for at least 10 uS.
**Note:** You can change the waveform style by **right clicking** the signal (e.g. data_in), and selecting the option `Waveform style -> Analog`, adjust your settings to improve the visualization in: `Waveform style -> Analog Settings` and change the **Interpolation style** to **Hold**.
4. Modify the DPP's parameters and see the change in the behaviour (op_mode_i, threshold_i, etc..).
5. Change the threshold values until you have only 5 pulses to be written in the FIFO (**Tip:** Check the *data_to_fifo* signal ).
6. Explore the different operation modes to understand their behaviour.
### Create a Block Design project.
7. Insert the **DPP_module_top_0.vhd** in the block design, making right click on it and selecting the option `Add Module to the Block Design`
8. Once the DPP module is inserted in the bd, connect the signals to a COMBLOCK as shown in the following figure:
**Note:** Try to undesrtand the purpose of each connection. Can the design be simplified?
9. **Generate Bitstream**, export it and create a **Vitis project** following the [overall project convetion](#overal-project-information-and-conventions).
10. Change the threshold and operation mode to obtain different outcomes.
# Digital Pulse Processor, Light version 1
In the previous section we got familiar with the concept of a DPP and the basic working principle of it.
This section will explore a more advanced one based on real data of the Electromanetic Calorimeter.
ECAL2 Pulses
This first version of the DPP is for processing pulses created
as the ECAL2 COMPASS detectors, the IP takes a stream of data
from a FIFO (Comblock FIFO Out), detects the arrival of a pulse
with a mean derivative and when its value (derivative) exceeds
ther threshold values defined by the user in runtime and, stores
the amplitude value in another FIFO (Comblock In) to be read
afterwards.
The DPP_0 block have the following Ports:
| Port | Type | Definition |
| ---- | ---- | ---------- |
| clk_i | Input | Clock Input |
| rst_i | Input | Reset Input |
| ena_i | Input | DPP_0 Enable signal |
| ADC_data_i | Input | Data Input |
|cf_1 | Input | FIR derivative coeficient 1 |
|cf_2 | Input | FIR derivative coeficient 2 |
|cf_3 | Input | FIR derivative coeficient 3 |
| threshold_high_i | Input | Detection Threshold of input over value |
| threshold_low_i | Input | Detection Threshold of input below value |
| op_mode_i | Input | Operation Mode* |
|delay_tap | Input | Delay counter |
| data_o | Output | Data Output |
| fir_wr_en_mux_out | Output | FIFO Write Enable/ Data Valid|
The four operation modes are the following:
| Operation Mode | Description |
| -------------- | ----------- |
| "00" | Amplitude acquisition |
| "01" | Input signal |
| "10" | Long FIR continuous output |
| "11" | Derivative FIR continuous output |
## Procedure
1. Follow the steps 1 to 5 from the [DPP_0 Procedure](#dpp_0-procedure) using the sources from `<easy_dpp_git_path>/dpp_1/src/`.
2. Import all the sources from `<easy_dpp_git_path>/dpp_1/simul/` and run a behavioural simulation for at least 10 uS.
4.**Generate Bitstream**, export it and create a **Vitis project** following the [overall project convetion](#overal-project-information-and-conventions).
5. Change the different registres and operation mode to obtain different outcomes.
# Project Ideas
1. Implement the programmable tap delay (This to control when the write enable should activate
the fifo writing) with a comblock resource
2. Implement a peak detector using only the derivative value
