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Laboratories Guides

  • Before Starting

  • Lab 1: Vivado-Design Flow for a Simple PS Design

  • Lab 2: GPIO IP Cores – PS Rd&Wr

    • Lab 2: Challenge

  • Lab 3: Custom IP

    • Lab 3: VHDL

  • Lab 4: External Interrupt SW-HW

  • Lab 5: Direct Memory Access (DMA)

  • Lab 6: Communication Block (ComBlock)

  • Lab 7: UDMA

  • Lab 8: ADC-DAC loopback and TCL

Project

  • Lab 2.1 SoC-FPGA Data Acquisition

  • Lab 2.2 Easy DPP

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Vivado Design Suite 2019.1 Installation Guide