https://gitlab.com/iccfpga-rv after the switch to RISC-V soft-cpu.Note: Main development moved to
Welcome to the iccfpga-core wiki!
Current project state:
IOTA core functions like address generation, signing, “Mini-Pow” and Proof of Work (PoW) need much computational power which makes it almost impossible (in a practical sense) to be done by small embedded systems. The aim of this project is to develop several modules that can be use by existing or new embedded applications needing IOTA core functionality. The first is an IOTA Core FPGA module which provides most IOTA core functions with hardware acceleration. It offers a high-level API which is easy to use whereas computationally intense low-level calculations are off-loaded to specialized logic which gives significant advantage in speed compared to a software-only solution – making it perfect for embedded applications. Additionally, the FPGA module implements several security mechanisms which will make it very hard for attackers to unauthorizedly gain access of seeds which are stored on the module. The second module will be a System-on-Module (SoM) which will use the FPGA module. This SoM will have enough resources to use it for a large number of applications and will run Linux. The SoM could be seen as an integration example for the FPGA module. It can be used unmodified for own applications but other microcontrollers could be using the FPGA module easily as well. The third module is an application board using the SoM which will be an IOTA sensor gateway for /dumb/ sensors.
Milestone 1: Proof-of-Work
Proof-of-Work was implemented in VHDL between 26th April '18 and 26th Aug '18 and became the PiDiver: https://github.com/shufps/iota_vhdl_pow
The PoW-core was later integrated into the IOTA Crypto Core.
Milestone 2: FPGA core and Arty S7 HAT
The FPGA-core was developed on an off-the-shelf Arty S7 (50k) board and can do the following:
- integrated Cortex M1 (32Bit ARM with 100MHz clock) which is programmable in C/C++. It also can be debugged via a standard debugging interface (SWD).
- it has accelerators for Trinary <-> Binary type conversions, Hashing (CURL-P81, KECCAC384, Troika; single clock-cycle per hashing-round) and can do Proof-of-Work very fast (~330ms avg).
- it does Seed management and can store up to 8 seeds in a secure memory
- it provides a JSON-Api which can be used via RS232. Currently it offers commands, for generating Addresses or random Seeds, signing Transactions and PoW — everything hardware accelerated.
- everything runs contained in the FPGA and the configuration file of the FPGA can be encrypted. It’s very easy to update the FPGA configuration but it’s impossible* to tamper with the microprocessor-code (which is embedded as ROM) or to extract sensitive information like keys. *: There is no “impossible” when it comes to security. But the encryption algorithm AES128 is unbroken.
Progress-reports on Medium:
Installing instructions: ICCFPGA-Installing
Arty S7 HAT (the green PCB on top of the Arty S7): Arty S7 HAT
Milestone 3: FPGA module
The FPGA module was developed for the FPGA-core from milestone 2.
- XC7S50 (FBGA196 package) Spartan 7
- 30x26mm in size
- Highly integrated step-down converter
- 128MBit SPI Flash (also used for the configuration of the FPGA)
- Microchip ATECC608A secure element
- Spare pins at the top of the module (16 I/Os)
- Several pins routed to the module connector (25 I/Os + JTAG)
Combined with the FPGA core from the second milestone, the I/Os on the module connector are used as following:
- JTAG for the FPGA
- SWD debugging interface for the Cortex M1 processor running inside the FPGA
- RESET for the Cortex M1
- Master-SPI with two dedicated I/Os for a W5500 ethernet controller
- Master-SPI (currently unused - perhaps it will become a SPI-Slave as faster alternative to UART)
- UART (115.2kBaud)
- 4 inputs and 4 outputs
Additionally there are 16 unused I/Os at the top of the module.
FPGA-Core installing instructions: ICCFPGA-Installing
Milestone 3: DEV-Board for FPGA module
Additionally, a "dev"-Board was developed. It was needed for testing the FPGA module and also testing some other things like bootstrapping the FPGA without proprietary tools.
It can run stand-alone (together with the FPGA module) because it has an ethernet controller on the board.
Milestone 4: Linux SoM
The heart of the SoM is the ATSAMA5D27 microcontroller from Atmel/Microchip. It can do the following:
- Cortex A5 SoC with 500MHz, 128MB embedded DDR2 RAM, full Linux support
- socket for the IOTA Crypto Core FPGA Module
- 8MB QSPI-Flash (on-the-fly encryption supported)
- 10/100MBit Ethernet
- High-Speed USB Host + Device
- µSD-Card interface
- several interfaces (I2C, SPI, UART)
- size of 83x36mm
Linux installation: link
Milestone 5: Gateway
- UBlox Sara G340 for mobile internet
- Wi-Fi, Bluetooth
- 10/100MBit LAN
- Highspeed Host + Device
- Mini DIN 8 with SPI, I2C (configurable)
The CO2-Sensor is a sample sensor for showing the feasibility of the whole gateway concept.
It uses a nRF52 module (UBlox NINA B112), a CO2 sensor (Sensirion SCD30) and an E-Paper display (Waveshare).
The sensor is connected via BLE (Bluetooth Low Energy) and low6pan (IPv6 via Bluetooth) to the Gateway and publishes MQTT pakets. A software running on the Gateway subscribes to the MQTT-topic and uses the FPGA-module for efficiently building IOTA Data transactions which are then sent to the tangle.