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[ARM / AArch64 / Bug Fix] Missing shifter operands in AND/CMP -> TST optimisation

J. Gareth "Kit" Moretonrequested to merge
CuriousKit/optimisations:arm-and-tst-fix into main

Summary

This merge request fixes a bug in the AND/CMP -> TST optimisation where the shifter operand, if present, would not be transferred over to the TST instruction, causing bad code to be generated.

System

  • Processor architecture: Arm, AArch64

What is the current bug behavior?

AND/CMP pairs that get optimised to a TST instruction, where the AND has a shifter operand as part of the last parameter, would not get included in the final TST instruction.

What is the behavior after applying this patch?

The shifter operand is now included as part of the TST instruction.

Relevant logs and/or screenshots

The main faults turned up when compiling Lazarus. Within the RTL, compiler and packages, a few examples turn up in the dialogs and udialogs unit. In the latter, for example (aarch64-linux, -O4) - before:

	...
.Lj1705:
	ldrsh	w0,[sp, #108]
	ldrh	w1,[sp, #32]
	tst	w1,w0
	b.eq	.Lj1707
	ldrsh	w0,[sp, #112]
	add	w0,w0,#1
	strh	w0,[sp, #112]
.Lj1707:
	ldrsh	w0,[sp, #108]
	ldrh	w1,[sp, #32]
	tst	w1,w0
	b.eq	.Lj1709
	ldrsh	w0,[sp, #112]
	add	w0,w0,#1
	strh	w0,[sp, #112]
.Lj1709:
	...

After, some omitted shifter operands are revealed:

	...
.Lj1705:
	ldrsh	w0,[sp, #108]
	ldrh	w1,[sp, #32]
	tst	w1,w0,lsl #2
	b.eq	.Lj1707
	ldrsh	w0,[sp, #112]
	add	w0,w0,#1
	strh	w0,[sp, #112]
.Lj1707:
	ldrsh	w0,[sp, #108]
	ldrh	w1,[sp, #32]
	tst	w1,w0,lsl #3
	b.eq	.Lj1709
	ldrsh	w0,[sp, #112]
	add	w0,w0,#1
	strh	w0,[sp, #112]
.Lj1709:
	...

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